Method and device for transmitting bivalent signals

ABSTRACT

The invention is concerned with a coding of telegraphic transistions based on the marking of the instant of a transition within the framework of a division of the definite sequence of the signals into sections having a fixed length shorter than the shortest possible duration of a stage without transition. These sections are subdivided into intervals; the order number of an interval where a transition has taken place is transmitted into reflected binary code, which assures a certain number of advantages.

United States Patent 1191 Oswald Aug. 21, 1973 METHOD AND DEVICE FOR TRANSMITTING BIVALENT SIGNALS [76] Inventor:

Brosse, 78 Versailles, France [22] Filed: Apr. 2, 1970 [21] Appl. No.: 25,120

[30] Foreign Application Priority Data Apr. 2, 1969 France 6910102 [52] US. Cl. 340/347 DD, 178/D1G. 3, 235/92 R, 235/92 CV, 235/92 T [51] Int. Cl..... H03k 13/00, H03k 13/24, H041 3/00 [58] .Field of Search 340/347 AD, 347 DD, 340/204, 206, 353; 332/9; 328/48, 50, 108,

235/92 T, 92 TF; 178/D1G. 3

Jacques Oswald, 1 rue Salomon de 3,210,756 10/1965 Flood ..340/347 DD 3,510,632 5/1970 Strandberg 235/92 TF 3,538,247 11/1970 Quinlan et a1. 178/6 DIG. 3

OTHER PUBLICATIONS Millman & Taub, Pulse & Digital Circuits, McGraw-l-lill, 1956, p. 411.

Susskind, Notes on 'A-D Conversion Techniques,

1959, pages 3-11 to 3-17.

Primary ExaminerMaynard R. Wilbur Assistant Examiner-Thomas J. Sloyan Attorney-Craig, Antonelli & Hill [57 5 ABSTRACT The invention is concerned with a coding of telegraphic transistions based on the marking of the instant of a transition within the framework of a division of the definite sequence of the signals into sections having a fixed length shorter than the shortest possible duration of a stage without transition. These sections are subdivided into intervals; the order number of an interval where a transition has taken place is transmitted into reflected binary code, which assures a certain number of advantages.

16 Claims, 7 Drawing Figures )H g V 9 11 (600p) PATENIED M m SHEEI-1-0F 4 FIG. 1

FIG. 2

(so) (sol I1 (600p) F|G.3

FIGS

llll

PATENTED MIB 2 1 I913 SHEU 2 OF 4 FIG. 4

e u 0 1 0 001111000011110000111100 W 0000I111 .|1..l.| 0000000 1 1 1 1 1 1 1100 0 m 00000000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00000000 0 1 1 I 1 1 1 1 1 1 1 1 1 1 1 1 000 0000000000 O 00 c 1 1 1 1 1 1 111 1 I 1 1 1 1 1 1 1 1 I 1 1 1 1 1 1 1 1 a n i w W23 I 2345678901234567 01234 789 5 3333333344444444445555555555mEH e m 00 .0111100001111 V CON O 1 1 1 1 1 1 11 00000000111 11110000 d 1 1 1 1 1 .111111 0000 n 0000000000 000 00 1 1 1 1 I 1 1 1 1 1 1 1 1 1 11 Q 00. 00000000000 0000000 00000000000 v l "23456 890 234567 9012345678901 111.11111112 222222222 mfimmmm um 3754.238

same or 4 BISTABLE FIG. 6

FLIP-FLOP MONO DECODER BINARY COUNTER TRANCODER REGISTER PATENTEBMJBZI ms 3754.238

saw u (If 4 FIG. 7

' SHIFT DECODER REGISTER QZOMPARATORS TRANSCODER Y COUNTER ZERO TION DECODER 76 COUNTER MONO.

METHOD AND DEVICE FOR TRANSMITTING BIVALENT SIGNALS The present invention relates to a method for transmitting two-level signals, for example, the type of signals employed in telegraphy or in the transmission of information by coded pulses. The present invention also relates to particular wiring connections being used for transmitting and for receiving the signals according to this method. I

Known under the name of modulation by coded pulses MIC, i.e., pulse-coded modulation, (PCM), is a method of modulation consisting of taking at regular intervals, samples of the low-frequency signal to be transmitted and in quantizing these samples with respect to a grid or matrix having a level practically always on a binary base, or 2" level. This gives rise to a train of n pulses, each of which, having a position identified as i, has a weight 2' corresponding to the position thereof. The MIC or PCM method is, thus, essentially a method of numerical coding of instantaneous quantized levels and of transmitting the code in the formof pulses, most often in the form of a train of series pulses, with means for separating the successive trains, coding the successive samples of the level and for identifying thereby the equilibrium or balance of each pulse of one train by its position in the train. I g

In the systems of telegraphy and transmission of numerical data, the signals are generally in the form of two-level waves whose polarity changes periodically at ensures continuous possibility of variation of the position of these transitions. From this point of view, the

with a margin of operation close to 100 percent,-

smaller than a previously determined value and as am all as is desired. Moreover, the telegraphic distortions are not cumulative, no matter how many systems are arthe frequency of the modulation. The information to be transmitted is, therefore, presentin the form of marks having a logical value 1, of variable duration, uncertain distribution and separated by stages having a logical value 0. The beginning of one mark constitutes a transition from zero to one or minus to plus. The end of one mark constitutes a transition from one to zero or plus to minus. The transmission of such data in numerical form follows the time of each transition and the direction thereof.

In the majority of cases, the duration of the various signals having a given level or state (0 or 1, or either negative or positive) is a multiple of an interval of'time or moment of duration T.; The transmitting systems convey these signals either in original form or in the form of modulation of a carrier wave. In synchronous operation, the transitions are produced at all'times at instants separated by multiple intervals of vT; on the other hand, inan asynchronous or arythmic system, there is no absolute mark or basis of reference for the time period of the transitions. Theprincipal advantage of the synchronous systems consists in admitting by vir-" tue the use of signal regenerators, very important margins of distortion reaching almost 100 percent. On the other hand, they are very rigid and can function only at agiven rate, which can be inconvenient in many applications. The arythmic or asynchronous systems are, instead, much more flexible and oftentimes it is possible to have the systems operate at different rates without a modification of the equipment. They correspond equally to the cases of use very frequently encountered. But on the other hand, the distortions caused by the transmission channel cannot be integrally compensated and the operating margins are much more reduced. In a general manner, the transparence of the systems; i.e.,the ability thereof to restore the telegraphic transitions to their position, whatever that position may be,

ranged in tandem.

SUMMARY OF THE INVENTION According to the present invention, a technique for coding a two level signal of the type used in telegraphic and assimilated signals having the form of marks in the form of zeroes and ones or pluses and minuses and being of variable duration, separated by transitions, the shortest possible duration between transitions being at least equal to, a specific duration T, comprises a division of the time into equal intervals or sections having a fixed duration 6 smaller than the aforementioned shortest possible duration T. Further, each of these intervals is subdivided into an integral number n of subintervals being equalwith respect to each other which receive a number according to their position'in the interval and the incident signal is sampled by short pulses delimitingthese subintervals. The indexing of a transition possibly occurring within an interval between twosamplings is made on the basis of the number of the position of the corresponding subinterval. Since the duration of one portion 9 is shorter than the duration T of the shortest possible mark, the result is that in one section or portion there is never more than one transition; i.e., there is either 0 or 1.

According to another characteristic of the present invention, in the case where. one interval possesses a permanent level or state without transition, the coding comprises an indexing characterizing thisstate or level, or a total of two fixed indexings for the two possible levels or states. Y

According to a further characteristic of the present invention, the numerical value of one indexing isfurnished in the form of succession of balanced and uniformly distributed pulses during the interval following' the indexing at a slower frequency than the samplings.

According to a still further characteristic of the present' invention, the code used for the indexing is'the. re-

- flected binary .code, with k binary digits, and thesampling pulses delimiting the aforementioned subintervals are numbered from 2 to 2" 3, the combination 2" -2 serving for indexing a permanent level during a past interval, and the combination 2" l serving for indexing the other permanent level, whereas the combinations 0 and l are not utilized for the indexing.

Finally, according to another characteristic of the present invention, the synchronization of the code is assured by the identification of the combination of the code having the highest numerical value (2* 1) which is the only one to comprise a binary digit of the value 1 followed by 10-1 binary digits having the value 0.

The foregoing description showsthe advantages of the principle proposed by the present invention. In fact,

the information is entirely coded so that the identification of the elements of the code is necessary, but equally sufficient, for determining the position of the transition with a previously assigned precision. With six code pulses, the distortion does not exceed 1' l.5 percent, whatever may be the deformations of the signals of the code themselves (as long as they remain indentifiable). Until the discrimination threshold is attained, the performances do not depend upon the signal/noise ratio. One can transfer the code by several transmission paths in tandem without supplementary degradation. The margin" is close to 100 percent because the distortion remains constant as long as the code is identifiable and conveniently assigned to the interval to which it is allotted. It is seen furthermore that the system is completely transparent and can operate at any telegraphic frequency smaller than that which corresponds to the duration of the interval.

This system is the transposition for the numeric or telegraphic signals of the pulse-coded systems of the telephonic signal in MIC or PCM. As a matter of fact, it is no longer the amplitude which is coded, but the position within the period of the telegraphic transition.

' One thus finds the same advantages as those well known in MIC or PCM systems. But, as in the case of the latter, the advantages acquired result in an increase of the necessary band width. In the case dealt with above, one substitutes six code pulses for an interval slightly shorter than the moment of telegraphic transmission. One thus multiplies, roughly, the band width bysix. The numerical example which has been treated here shows that the frequency of recurrence of the code pulses is 10 kHz for the coding of a sequence whose rapidity is 1,500 Bauds.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention will now be further described hereinafter on the basis of and with reference to the accompanying drawings, wherein FIG. 1 illustrates a sequence of signals divided into sections having one interval as their duration;

FIG. 2 shows a portion of FIG. 1 in an enlarged scale with the identification of one transition within a subinterval;

FIG. 3 illustrates in a further enlarged scale, the passage of one interval to the next following interval and the corresponding counting operations;

FIG. 4 is a table of the reflected binary code, or GRAY code, used in the invention;

FIG. 5 shows the-pulses coded for the indexing of the transitions of the signal of FIG. 1;

FIG. 6 is a diagram of one embodiment of a coder according to the present invention; and FIG. 7 is a diagram of an embodiment of an associated decoder.

' DETAILED DESCRIPTION FIG. 1 represents a sequence of arbitrary two-level signals, such as a telegraphic transmission or any transmission of numerical data. The only presumption which is made is that any signal of a given level or polarity (positive or negative) has a duration longer than or equal to a known duration T.

The sequence of signals M to be transmitted is subdivided into equal elementary intervals having a unitary duration 9 T, succeeding each other indefinitely, the origin of the times being absolutely whatever may be desired, which is to say that the beginning of each interval is without correlation with the transitions of the signal. In FIG. 1, the intervals represented are numbered I I, I L I It should be understood that it is here a question of an extract from a sequence which can be extended on both sides. By way of example it has been assumed that this is a telegraphic transmission at a speed of manipulation of 1,500 bauds. In other words, thetelegraphic moment has a duration of 666 us, the duration T mentioned above. Under these conditions, and still by way of a non-limitative example one chooses for the duration 9 of one section 600 psec.

The considerations for the choice of 6 for a given T will be expounded hereunder.

There is a transition to 6 in the section I a transition to 6 in section I, no transition in section i a transition to 8 in section I a transition to 8 5 in section I,

Beneath each transition a number has been shown: 21 opposite 8 1 27 opposite 6 2 40 opposite 6 4 47 opposite 8 Opposite I being without transition, there is shown a which is effectively the permanent level of the section I,

The number appearing opposite one transition is the position of the pulse taken, serving for sampling the signal M which immediately follows this transition. This definition will be further explained hereunder with reference to FIG. 2. i I

Shown in FIG. 2 at a larger scale is the section I, of FIG. 1.

This section is subdivided into 60 subintervals O having a unitary duration of 10 pa These intervals with the duration 9' are delimited by short sampling pulses marked in FIG. 2 by fine vertical strokes. By a short pulse is meant a pulse beingmuch shorter than the interval G for example having a duration between 0.5 and 0.8 us. The first pulses corresponding to the level or polarity are low or reduced in amplitude. The others, corresponding to the valence mark are high. Shown at one point in FIG. 2 are the pulses arriving at the times 10 9, 20 6', 30 6, 40 6, 50 9, 60 9. These numeric values are not generally the numbers of the order of the pulses, there is a shift by one unit One will see why this is so by referring to FIG.

The transition 7 1 occurs between the 19th pulse and the 20th pulse. It is placed in evidence by the inversion of polarity of the sample taken by the 20th pulse as compared to the polarity of the sample taken by the 19th pulse. The 20th pulse bears the order number 21.

The transition 7 1 is indexed 21; this is the transmission of the numerical value 21 by series pulses coded in binary form which constitutes the transmission of the moment of the transition. As far as the direction is concerned, it is evidently known if the previous polarity is known. It will be noted that the technique is protected against false polarities by a significant safety factor.

Since the number of distinct numerical values to be indexed and transmitted is between 32 and 64, it is here a question of a coding at six binary digits with a maximal capacity of 63.

The six binary digits representing an indexing value are fed in line in the course of one interval in the form of pulses being balanced according to their position; for a complete message, pulses form a uniform spacing unit FIG. 3 shows at an even larger scale the zone of passage between a section In and the next following section Ik 1 The last pulse taken from the section In is marked 61; the next-to-the last, of an earlier instant of ts is s 60, the preceding one 59, and so forth. The first pulse taken from the section I 1 bears the number 2, the next one number 3, and so forth.

The penultimate subinterval of the section 1,, has been designated with S the last one with S the first subinterval of the section 1,, is identified as S the second one as S, etc.

The first subinterval S is subdivided into four segments having a unitary duration 9" equal to 2.5 ps by pulses at the positions 62, 63, l, 2. The positions 62, 63 are indicated by auxiliary pulses, the state 2 is indicated by a normal sample pulse. The state 0 is not formed (see FIG. 6 below).

If a transition has occurred in the course of the interval 1,, one transfers the combination of the code characterizing the transition. If no transition has appeared within the interval I no code has been transferred when the pulse No. 61 arrives. In this case according to the polarity of the signal, one transfers either the combination 62 (positive valence or state), or the combination 63 (negative valence or state). The values 62 and 63 are transferable. The values 0 and l, on the other hand, are not transferrable. The first transferrable value after 63 is 2 (first value of the section 1,, The reason therefor will be explainedrin connection with FIG. 4.

FIG. 4 is a table of the numerical values from 0 to 63 coded in reflected binary code, also called Gray code.

In connection with the description of one example of a device for carrying out the method proposed by they present invention it will be noted that the coding of the position range or of one transition is carried out with the aid of a counter which counts the sample pulses, which is returned to zero at the beginning of each interval and the content of which is cleared and transferred when a transition appears. For the reasons which will be further explained below, one will substitute for the natural binary code, furnished directlyby the counter,

the reflectedbinary code in whichitwo numbers of an.

adjacent range row differ only by a single binary digit. In fact, the properties of this reflected binary code may be used to good advantage in order to indicate not only ,the positions of the transitions within one interval,but

equally the polarity ofthe signal and the beginning of the sections(synchronization of the code element).

These different data are indispensable in order that the receiver may correctly restore the signal having been coded by the encoder.

The table of FIG. 4 recalls the combinations of the reflected binary code in a numbering increasing from 0 to 63 (for the case which has been choses as example there are six binarydigits, but the properties utilized are absolutely general and directly transposable, whatever the number of digits of the code).

According to the process of the present invention, the following rules serve for the use of the code:

a. From among the 64 available combinations, only are used for designating the 60 subintervals, from S, to S see FIG. 3 above. The transfer of one of these combinations indicates that there has been achange of polarity transition in the previous subinterval.

b. The combination 0 (000000) is not formed; the combination 1 (000001) is formed but not transferred. Accordingly, among the transferred combinations, only the combination 63 contains 5 successive zeros.

c. The combination 62 (100001) indicates an absence of transition in the previous interval with positive polarity, for example (permanently positive).

d. The combination 63 (100000) indicates an absence of transition in the previous interval with negative polarity (permanently negative).

Within an indefinite sequence of code combinations which succeed each other in regular fashion and without separation, the combination 63 permanently negative at least in the interval considered is identifiable without any ambiguity, which renders it possible to synchronize the code at the reception thereof, that is to say, to recognize the first digit of each group of six binary digits forming a code. In fact, except for the combination 63 it is impossible to find a sequence composed of one 1" followed by at least five zeros.

In order to prove this, the different cases possible will be described.

The first involves two successive transitions within two adjacent intervals. Sincethe duration of the interval is shorter, hypothetically, than the shortest interval which separates two successive transitions, the result is that the position of the transition in the interval I, l is of necessity greater than the position of. the transition of the interval 1,, and it is clear according to-the table that a succession of two digits of increasing orders or ranges cannot comprise or contain more than four zeros; as for example, 3-4, 3-5, 7-8, etc. In this first case it is thus impossible to encounter a sequence of l and of five zeros in a row. As a second case permanently a positive interval may be framed or enclosed by two each time one encounters a negative polarity intervalv not containing a transition. This eventuality will be pro duced without delay even if the negative signals are all of a minimal duration, because the interval is shorter than any elementary signal and since there is no, synchronization between the basis of time of samplingand the analyzed signal. l

It is seen that the use of a Gray code combined with the process of the present invention affords remarkable facilities for the synchronization of the code received at the level of words, that is to say, the identification of 1: positions of balanced pulses which index 'one transmission within an indefinite sequence of pulses. However, the process of the present invention is applicable to another code, but this involves a complication of the apparatus and a capacity loss in transmission.

FIG. 5 represents, symbolically and at a regular spac-. ing between the pulses coding different weights,.the

successive codes which are characteristic for the signal The principle described hereinabove is general since I the number of binary elements of the code does not in-- tervene. If, for example, one is content with a code with four binary elements, one disallows the two combinations 0000 and l 0001 and one reserves the combination 14 1001 and 15 1000 for the identification of the intervals without transition possessing a given polarity. The subdivision interval is then divided into twelve subintervals, which allows for limiting the systematic distortion to i: 8 percent approximately. The combination 15 is the only one to have three zeros following a 1 and the same method may thus be employed for the synchronization of the code.

DETERMINATION OF THE INTERVAL 9 The previous example relates to a case with weak distortion. For a nominal duration of the telegraphic moment of 666 ts, one admits that the real duration always remains clearly higher than 600 [LS in all instances.

But in the general case it may happen that the intensity of the possible distortions is much higher and forces one to provide a smaller subdivison interval. It may therefore be wise to take as the sectioning interval an interval which is equal to half of the nominal period or even a little shorter than that.

But this is made at the expense of the band width, which is thus found to be extended.

As'a matter of fact, in the previous example, the transmission of the information is made in the form of six binary positions in 600 ,us or a band width, roughly speaking, in the order of 10 kHz. If one divides the duration of the interval by two for 30 subintervals per interval, one will have to transmit five binary positions per interval, or five pulses in 300 [L5, or 10 pulses in 600 [L- The band width is thus multiplied by /6.

FIG. 6 is a logic diagram, given as an example of a coder furnishing a coding of the transitions according to the technique previously described.

1 l, 12 and 13 are bistable flip-flops.

l4, l5 and 16 are monostable flip-flops; 14 and 15 give a delay of 2.5 [1.8, 16 gives a delay shorter than 6 21, 22, 23 are AND circuits with two inputs; while 24, 25, 26 are OR circuits.

41 is a modulo 2" circuit, or an exclusive OR cir-- cuit. 1

42 is an oscillator furnishing at its output clock pulses H; in the case of the example, the frequency chosen for the H pulses is 100 kHz.

43 is an element for synchronizing on the H pulses a train of indefinite H .pulses having a lower frequency than the H pulses whose role will be explained below. In the present case, the element 43 is a simple divideby-lO circuit.

44 is a binary counter with six binary digits; 45 is a decoder decoding the conditions 61, 62, 63 of the counter 44; 46 is a storage to which there is transferred the condition of the counter 44 under the command of a pulse appearing at D at the output of the AND circuit 26; 46 is a natural binary reflected binary transcoder receiving the content of the storage 46; the transcoded signals are transmitted to the output shift register 49 by AND circuit 48 under the command of a pulse appearing at F at the output of the monostable flip-flop l6.

, The H pulses are applied to the advance line of the shift register 49. The balanced pulses for indexing are received on the terminal S.

The operation of the circuit of FIG. 6 is as follows.

The counter 44 counts through the conditions 2 to 61 under the command of the H pulses spaced by 10 us transmitted by 24. The condition 61 decoded by causes a pulse to be generated which energizes the monostable flip-flop 14, which in turn, furnishes an output pulse delayed by 9' =2.5 us (see FIG. 3). This pulse is reinjected into the counter 44 by 24 and causes it to advance to 62.

The output pulse of 14 is again re-emitted by 15 with a delay of 9' =2.5 [1.8; the output pulse of 15 is, in turn, re-injected by 24 into the counter which advances to The output pulse of 15 is re-emitted with a delay of 2.5 [L8 by 16; there issues at F a pulse for resetting the counter to l. The condition 0 is never posted by the counter. It is for this reason that the position has been omitted from FIG. 3.

The signal M to be transmitted is applied at E to the input of the flip-flop 11 which is a recopying flip-flop and receives moreover the clock pulses H. The condition of the output A of 1 1 is applied to exclusive OR circuit 41, as is the outputcondition of the flip-flop 12, which receives on the one hand A and on the other hand the clock pulses H. The group 11, 12, 41 serves for comparing the polarities of two consecutive samplings of the signal M carried out at the frequency H.

If a change of polarity (transition) appears, an output pulse from 41 transmitted at D by 26 causes the condition of the corresponding counter to be entered into storage 46. The pulse D resets the flip-flop 13 to zero which therefore does not transmit anything by 23 through 26 and D in the case where a transition has appeared in the interval.

If there has been no transition in the interval when the condition 61 of the counter appears, the flip-flop 13 is set. The AND circuit 23 is thus conductive. One of the conditions.62 or 63 transmitted by 25 is thus transmitted at D. The state or condition 62 is transmitted by 21 for A 1 (positive polarity); condition 63 is transmitted by 22 for A 1 negative polarity The pulse F resets the flip-flop 13 at the end of each I interval. The balanced pulses are delivered in series by the output register 49 at a rate H slower than the sample rate. In the PCM process it is the opposite: the balanced pulses are delivered at a faster rate than the samplings. I

FIG. 7 shows a diagram of a receiver decoding the signals received from an emitter of the type shown in FIG. 6.

The signals being coded in reflected binary code and arriving on a terminal E are received in a shift register 51 which is associated with a decoder 52 having the conditions 62 or 63," and with a reflected binary codenatural binary code transcoder 53. The content of the transcoder 53 may be transferred into a storage 55 by a unit of six AND gates 54. A group or unit of six comparators 56 (modulo 2 circuits or exclusive OR circuits) serves for comparing the characters in storage to the conditions of the flip-flops of a counter 57 having .capacity 63, which receives at the input thereof the clock pulses H having the same frequency as the H pulses of the coder (FIG. 6), which are obtained as will be seen hereinbelow,

58 is a capacity counter 5 which is associated with a zero position decoder 59. The counter 58 receives H pulses having the same frequency as the H'pulses of the coder (FIG. 6).

' counter 58.

73 is an AND circuit having six inputs which transmit a controlling pulse to an output flip-flop 74 having an output terminal S on which there is found again the signal transmitted upon the command of the six comparator circuits 56.

The output terminal 63 of the decoder 52 is connected to a resetting to zero input of the counter 58. It is also connected to a resetting to 1" terminal X of the output flip-flop 74.

The output terminal 62" of the decoder 52 is connected to one input of an AND gate 75 whose other input receives a signal from the zero position decoder 59. The output of this AND gate is connected to a resetting to zero input Y of the flip-flop 74.

The output signal of the decoder 59 is also transmitted with a slight delay given by a monostable flip-flop 76- to the input of the six AND gates 54 and to the resetting to zero terminal of five of the stages of the counter 57 to six stages, thus effecting a resetting or return to l of the condition of the counter.

76 is a monostable flip-flop which has the purpose or function of delaying the transmission of the output signal of the decoder 59 for the time necessary for the propagation in the elements 53, 54.

The operation is as follows.

The clock 71 carries out the synchronization at the level of sampling. The counter 57 is a counter of the sampling time and the decoder 59 effects the synchronization at the level of the word of six characters.

At each through zero of the counter 58, the decoder 59 emits a signal which, delayed by 76, is applied for transfer to the AND gates 54 and in for resetting to the 1 condition of the counter 57.

The sixcode pulses stored inthe register 51 are transcoded from reflected binaryinto natural binary code by the transcoder 53, and then transferred by the AND gates 54, at the beginning of the interval following the arrival of the complete .combinationof the code, to the storage register 55. The counter 57 which advances at The installation could operate according to a code different from the reflected binary code, for example, in the'natural binary code. But in this case the synchronization of the decoder would be much more laborious and costly in capacity of transmission. The use of the reflected binary code such as it is employed allows for using the invention to its best advantage.

Within the framework of the present invention, it is possible to transmit, over several telegraphic paths, having either the same telegraphic frequency or a different telegraphic frequency, by means of the same process of sub-dividing the time into intervals, which are counted according to a reflected binary system by using an apparatus of the type described above.

I claim:

1. A system including a coder portion and a decoder portion for respectively coding and decoding a bi-level incident signal having binary states of variable duration, the shortest time period between transitions from the frequency of the H pulses counts through the numbers from 2 to 61 and'the comparator 56 verifies, binary digit by binary digit, to which number appertains the code in storage. The instant at which the counter reaches the combination according to the code in storage causes the'condition of the output flip-flop 74 to change; hence the regeneration at the desired instant of I the telegraphic transition.

'When a permanently negative condition 63 will be present, a signal of resetting to l is applied directly to the flip-flop 74.

When a condition 62 (permanently positive) is present at the same time as a zero decoded by the decoder 59 (synchronism reached), 8 signal for resetting to zero is applied directly to the flip-flop 74 by the gate 75 The conditions 6 2, 63 and 0 are never counted by the counter 57.

one binary state to another being a specified duration T, said coder portion comprising:

means for generating a series of clock pulses at a freq s y means, responsive to the receipt of said'clock pulses,

for sampling said incident signal at the frequency of said clock pulses;

means, responsive to said sampling means, for comparing the levels of two successive samples of said signal; 1

means, having k binary stages, k being a positive integer, for counting said clock pulses within a predetermined range in a recurrent manner, said counting starting at a position n, where n is a positive integer, in the course of an interval 6 which is shorter-than the shortest duration T during which the level of an incident signal remains constant, such that thepulses employed by said sampling means are spaced by a duration of approximately 6 l2" a memory having k binary locations;

. means, responsive to the absence of the occurrence of a level change in the course of said interval, for

storing, in said memory, data representative of a prescribed count identifying said level as well as the absence of a change thereof; and

the contents of said counting means in response to the output of said comparing means produced upon the occurrence of different levels for two successive samples whereby the occurrence of a change in the level of two successive samples of said signal is indexed according to theposition of said level change within the interval.

2. A system including a coder portion and a decoder portion according to claim 1, said coder portion further including means, responsive to said clock pulses, said clock pulses having a frequency H, for converting said clock pulses into a series of pulses which have a fre-,

quency H and for shifting the contents from the k locations of said memory in parallel form at a uniform spacing of 1r 9/k and converting said contents into a serial form signal in response to said series of pulses having a frequency H.

3. A system including a coder portion and a decoder portion according to claim 1, said coder'portion further including means for generating three successive pulses during a sub-portion of said intervals 9 between the transfer means for transferring into said'memo'ry last sampling pulse of the interval and the first sampling pulse of the next following interval; and

means for introducing the first two of said three pulses into said counting means and for resetting said counting means in response to the third pulse of said three pulses.

4. A system including a coder portion and a decoder portion according to claim 2, said coder portion further including a means coupled between said memory and said shifting means for transcoding natural binary coded signals into reflected binary coded signals.

5. A system including a coder portion and a-decoder portion according to claim 4, said coder portion further including means responsive to said transcoding means for transferring the contents of said memory which have been transcoded into reflected binary code into said converting means once per interval 9, in response to the resetting of said counting means.

6. A system including a coder portion and a decoder portion according to claim 5, said coder portion further including a first decoder connected with said counting means and having three outputs, the first one of which is connected to the input of a three stage delay circuit, whose total delay is less than B/k, the output of the third stage delivering a pulse for'resetting said counting means. I

7. A system including a coder portion and a decoder portion according to claim 6, wherein the first and second stages of said delay circuit are connected to said counter through a logic circuit which receives said clock pulses, whereby the first pulse in an interval causes the counting means to advance from a count of l to 2 and subsequent pulses cause said counter to advance from 2 to l n 2" 3, while the pulses received from the first and second stages of saiddelay circuit causes said counting means to advance from 2" 3 to 2" 2 and 2" -2 t 2" -l, respectively.

8. A system including a coder portion and a decoder portion according to claim 7, said coder portion further including means responsive to a signal generated by one of said comparing means and the two outputs of said first decoder for supplying a transfer signal to said memory.

9. A systemincluding a coder portion and a decoder portion according to claim 8, wherein said means for supplying a transfer signal includes an exclusive-OR circuit coupled with a logic'circuit for preventing a transfer signal from being transmitted to said memory if said exclusive-OR circuit has emitted a transfer signal to said memory during said interval.

10. A system according to claim 2, including a coder portion and a decoder portion, said decoder portion having means for converting said serial form signal into a bi-level output signal comprising a shift register made up of k-stages for receiving said serial form signal, a receiver clock generating a series of clock signals connected to said shift register for controlling the shifting of said serial form signal into said shift register, a receiver decoder connected to the respective stages of said shift register for detecting when the contents of the stages of said shift register are representative of one of the numbers 2" l and 2" 2 and providing respective signals indicative thereof and further including a receiver transcoder for converting the contents of said shift register from reflected binary code into natural binary code.

11. A system including a coder portion and a decoder portion according to claim 10, said decoder portion further including a memory and a receiver transfer means connected to said transcoder for storing the outputs thereof, a receiver counter coupled to said receiver clock for counting the clock signals generated thereby and a comparing means for comparing the contents of said counter with the contents of said memory and generating an output signal upon coincidence thereof.

12. A system including a coder portion and a decoder portion according to claim 1 1, wherein said comparing means includes k comparators, each having two inputs one of which is connected to a respective stage of said memory and the other to a corresponding stage of said receiver counter, and a AND gate having k inputs connected to the outputs of said comparators and an output flip-flop connected to the output of said AND circuit.

13. A system including a coder portion and a decoder portion according to claim 12, wherein an output of one stage of said receiver decoder is connected to said flip-flop, whereby said flip-flop will be reset to a 1 condition upon the decoding of the number 2"l, and another output of another'stage of said receiver decoder is coupled to said flip-flop, whereby. said flip-flop will be reset to a 0 condition upon the decoding of the number 2"2.

14. A system including a coder portion and a decoder portion according to claim 13, said decoder portion further including a synchronizing means having a counter with k stages, which receives pulses at a frequency H, which is reset to zero by said receiver decoder and is coupled to a zero position decoder for providing a transfer signal to said receiver transfer means and a signal for resetting said receiver counter.

15. A system including a coder portion and a decoder portion according to claim 14, said decoder portion further including means, responsive to the coincidence of a zero decoding produced by said zero position decoder and a decoding'of a sample condition by said receiver decoder'for resetting said flip-flop to zero.

16. A system including a coder portion and a decoder portion according to claim 15 said decoder portion further including a monostable flip-flop, inserted at the output of said zero position decoder, for delivering said transfer signal and the signal for resetting said receiver counter to l, for at least the length of time required for the remaining signals to be propagated within the-decoding means.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No.3, 754, 238 C Dated u.1g11si 2 l. l.9l3

Invent0r( Jacques Oswald It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Title Page, insert the Following:

Signed and sealed [this 16th day of AprilflQYLL.

(SEAL) Attest:

EDWARD PLFLETCERJ'R. Attesting Officer C. MARSHALL DANN Commissioner of Patents UNITED S'IATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No.3 754, 238

Dated A ngnsj; 21 1913 Invent0 Jacques Oswald I1: is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Title Page, insert the Following:

Signed and sealed this 16th day of A rilflw p.

(SEAL) Attest:

EDlIARD I LEETCHER,JR. Attesting Officer C. MARSHALL DANN Commie sioner of Patents 

1. A system including a coder portion and a decoder portion for respectively coding and decoding a bi-level incident signal having binary states of variable duration, the shortest time period between transitions from one binary state to another being a specified duration T, said coder portion comprising: means for generating a series of clock pulses at a frequency H; means, responsive to the receipt of said clock pulses, for sampling said incident signal at the frequency of said clock pulses; means, responsive to said sampling means, for comparing the levels of two successive samples of said signal; means, having k binarY stages, k being a positive integer, for counting said clock pulses within a predetermined range in a recurrent manner, said counting starting at a position n, where n is a positive integer, in the course of an interval Theta which is shorter than the shortest duration T during which the level of an incident signal remains constant, such that the pulses employed by said sampling means are spaced by a duration of approximately Theta /2k ; a memory having k binary locations; means, responsive to the absence of the occurrence of a level change in the course of said interval, for storing, in said memory, data representative of a prescribed count identifying said level as well as the absence of a change thereof; and a transfer means for transferring into said memory the contents of said counting means in response to the output of said comparing means produced upon the occurrence of different levels for two successive samples whereby the occurrence of a change in the level of two successive samples of said signal is indexed according to the position of said level change within the interval.
 2. A system including a coder portion and a decoder portion according to claim 1, said coder portion further including means, responsive to said clock pulses, said clock pulses having a frequency H, for converting said clock pulses into a series of pulses which have a frequency H'' and for shifting the contents from the k locations of said memory in parallel form at a uniform spacing of pi Theta /k and converting said contents into a serial form signal in response to said series of pulses having a frequency H''.
 3. A system including a coder portion and a decoder portion according to claim 1, said coder portion further including means for generating three successive pulses during a sub-portion of said intervals Theta between the last sampling pulse of the interval and the first sampling pulse of the next following interval; and means for introducing the first two of said three pulses into said counting means and for resetting said counting means in response to the third pulse of said three pulses.
 4. A system including a coder portion and a decoder portion according to claim 2, said coder portion further including a means coupled between said memory and said shifting means for transcoding natural binary coded signals into reflected binary coded signals.
 5. A system including a coder portion and a decoder portion according to claim 4, said coder portion further including means responsive to said transcoding means for transferring the contents of said memory which have been transcoded into reflected binary code into said converting means once per interval Theta , in response to the resetting of said counting means.
 6. A system including a coder portion and a decoder portion according to claim 5, said coder portion further including a first decoder connected with said counting means and having three outputs, the first one of which is connected to the input of a three stage delay circuit, whose total delay is less than Theta /k, the output of the third stage delivering a pulse for resetting said counting means.
 7. A system including a coder portion and a decoder portion according to claim 6, wherein the first and second stages of said delay circuit are connected to said counter through a logic circuit which receives said clock pulses, whereby the first pulse in an interval causes the counting means to advance from a count of 1 to 2 and subsequent pulses cause said counter to advance from 2 to 1 + n 2k - 3, while the pulses received from the first and second stages of said delay circuit causes said counting means to advance from 2k -3 to 2k -2 and 2k -2 to 2k -1, respectively.
 8. A system including a coder portion and a decoder portion according to claim 7, said coder Portion further including means responsive to a signal generated by one of said comparing means and the two outputs of said first decoder for supplying a transfer signal to said memory.
 9. A system including a coder portion and a decoder portion according to claim 8, wherein said means for supplying a transfer signal includes an exclusive-OR circuit coupled with a logic circuit for preventing a transfer signal from being transmitted to said memory if said exclusive-OR circuit has emitted a transfer signal to said memory during said interval.
 10. A system according to claim 2, including a coder portion and a decoder portion, said decoder portion having means for converting said serial form signal into a bi-level output signal comprising a shift register made up of k-stages for receiving said serial form signal, a receiver clock generating a series of clock signals connected to said shift register for controlling the shifting of said serial form signal into said shift register, a receiver decoder connected to the respective stages of said shift register for detecting when the contents of the stages of said shift register are representative of one of the numbers 2k -1 and 2k - 2 and providing respective signals indicative thereof and further including a receiver transcoder for converting the contents of said shift register from reflected binary code into natural binary code.
 11. A system including a coder portion and a decoder portion according to claim 10, said decoder portion further including a memory and a receiver transfer means connected to said transcoder for storing the outputs thereof, a receiver counter coupled to said receiver clock for counting the clock signals generated thereby and a comparing means for comparing the contents of said counter with the contents of said memory and generating an output signal upon coincidence thereof.
 12. A system including a coder portion and a decoder portion according to claim 11, wherein said comparing means includes k comparators, each having two inputs one of which is connected to a respective stage of said memory and the other to a corresponding stage of said receiver counter, and a AND gate having k inputs connected to the outputs of said comparators and an output flip-flop connected to the output of said AND circuit.
 13. A system including a coder portion and a decoder portion according to claim 12, wherein an output of one stage of said receiver decoder is connected to said flip-flop, whereby said flip-flop will be reset to a 1 condition upon the decoding of the number 2k-1, and another output of another stage of said receiver decoder is coupled to said flip-flop, whereby said flip-flop will be reset to a 0 condition upon the decoding of the number 2k-2.
 14. A system including a coder portion and a decoder portion according to claim 13, said decoder portion further including a synchronizing means having a counter with k stages, which receives pulses at a frequency H'', which is reset to zero by said receiver decoder and is coupled to a zero position decoder for providing a transfer signal to said receiver transfer means and a signal for resetting said receiver counter.
 15. A system including a coder portion and a decoder portion according to claim 14, said decoder portion further including means, responsive to the coincidence of a zero decoding produced by said zero position decoder and a decoding of a sample condition by said receiver decoder for resetting said flip-flop to zero.
 16. A system including a coder portion and a decoder portion according to claim 15 said decoder portion further including a monostable flip-flop, inserted at the output of said zero position decoder, for delivering said transfer signal and the signal for resetting said receiver counter to 1, for at least the length of time required for the remaining signals to be propagated within the decoding means. 